Oregon Patent of the Month – October 2024
MonolithIC 3D Inc. has redefined innovation in semiconductor design with its cutting-edge method for designing monolithic 3D integrated circuits (ICs). This groundbreaking approach leverages advanced Computer-Aided Design (CAD) tools to partition circuits into distinct levels—such as logic, memory, and RF—stacked vertically with seamless interconnections. Unlike traditional stacked-layer processes that rely on bulky and costly Through-Silicon Vias (TSVs), MonolithIC 3D’s method integrates ultra-dense vertical connections that scale naturally with semiconductor advancements.
The innovation lies in its precision. Using specialized CAD tools, designers can optimize placement and routing across levels with unmatched accuracy. For instance, the first level may host logic transistors processed on a different node than the second-level memory transistors, allowing unparalleled design flexibility. These tools synchronize the placement of inter-level connection pads, ensuring efficiency in both layout and routing.
MonolithIC 3D’s approach accommodates diverse functional requirements. The second level, often a memory-dominant structure, is modular and adaptable, enhancing versatility across applications. Additional levels can incorporate specialized features such as RF circuits or advanced input-output cells, making this technology ideal for modern, multifunctional devices.
By drastically reducing the size of inter-layer connections compared to TSVs, this method enables denser designs, lower power consumption, and enhanced performance. It represents a leap forward in 3D IC technology, unlocking new possibilities for compact and powerful chips in applications ranging from high-performance computing to energy-efficient IoT devices. With MonolithIC 3D Inc.’s innovations, the future of semiconductor design is here.
Are you developing new technology for an existing application? Did you know your development work could be eligible for the R&D Tax Credit and you can receive up to 14% back on your expenses? Even if your development isn’t successful your work may still qualify for R&D credits (i.e. you don’t need to have a patent to qualify). To find out more, please contact a Swanson Reed R&D Specialist today or check out our free online eligibility test.
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The Research & Experimentation Tax Credit (or R&D Tax Credit), is a general business tax credit under Internal Revenue Code section 41 for companies that incur research and development (R&D) costs in the United States. The credits are a tax incentive for performing qualified research in the United States, resulting in a credit to a tax return. For the first three years of R&D claims, 6% of the total qualified research expenses (QRE) form the gross credit. In the 4th year of claims and beyond, a base amount is calculated, and an adjusted expense line is multiplied times 14%. Click here to learn more.
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