Theoretical and Statutory Foundations of the Permitted Purpose Doctrine

The concept of a permitted purpose serves as the primary “Functional Test” within the broader regulatory architecture governing research incentives both at the federal level under Internal Revenue Code (IRC) Section 41 and the state level through Oregon’s specialized tax statutes. For an activity to be considered “qualified research,” it must be undertaken for a purpose that is inherently technical and functional. This requirement is the first hurdle in the mandatory four-part test used to evaluate the eligibility of research expenditures for tax relief. By focusing on the “why” behind the research, the permitted purpose rule distinguishes between activities that drive economic and technological growth and those that are merely operational or decorative in nature.

Under the Oregon Research and Development Tax Credit for Semiconductors, which was codified following the passage of Enrolled House Bill 2009 (2023), the state explicitly adopts the federal definitions provided in IRC § 41(d). The statute mandates that the research activity must be aimed at developing a new or improved business component. A business component, in the context of the semiconductor industry, encompasses any product, process, computer software, technique, formula, or invention that is held for sale, lease, or license, or used by the taxpayer in their trade or business. The permitted purpose requirement demands that the taxpayer’s intent be focused on achieving improvements in one of four specific functional categories: functionality, performance, reliability, or quality.

This functional focus is critical because it creates a clear legal boundary against excluded activities. For instance, research focused purely on aesthetic factors—such as style, taste, cosmetic design, or seasonal variations—is explicitly disqualified from being a permitted purpose. In the highly technical field of semiconductor manufacturing, this means that while the redesign of a chip’s physical architecture to improve thermal dissipation is a permitted purpose, the redesign of the chip’s branding or outer packaging for purely visual appeal is not. The application of this test requires a nuanced understanding of the technical objectives of a project, as the law seeks to reward the resolution of technical uncertainties through a process of experimentation rather than the application of established artistic or marketing principles.

The Evolution of Oregon’s R&D Tax Policy

Oregon’s legislative approach to research incentives has undergone a significant transformation in recent years, moving from a broad-based credit to a highly targeted sectoral incentive. For nearly three decades, the state offered a general Research Activities Credit under ORS 317.152, which was available to all corporations engaged in qualified research. This legacy credit provided a 5 percent incentive on increases in qualified research expenses, using a calculation method that closely mirrored the federal credit but with significantly lower caps and rates. However, the 2017 Oregon Legislature allowed this general credit to sunset, creating a multi-year vacuum in state-level R&D support.

The re-introduction of an R&D credit in 2023 through HB 2009 was not a restoration of the old general credit but a strategic response to the federal CHIPS and Science Act and a bid to maintain Oregon’s competitive position as a global center for semiconductor innovation. This new “Research and Development Tax Credit for Semiconductors” is codified in ORS 315.518 through 315.522 and is specifically restricted to “qualified semiconductor companies”. The shift in policy reflects a transition from subsidizing general corporate innovation to providing intensive support for a specific industry viewed as vital to the state’s economic infrastructure and national security.

The financial structure of the current semiconductor credit is substantially more robust than its predecessor, offering a 15 percent credit on excess qualified research expenses, which is a three-fold increase over the legacy 5 percent rate. Furthermore, the maximum allowable credit per taxpayer was increased to $4 million per year, reflecting the capital-intensive nature of semiconductor R&D. This legislative evolution demonstrates Oregon’s recognition that in the semiconductor industry, the “permitted purpose” of research often involves multi-billion dollar investments in new process nodes and fabrication techniques that require significant state-level offsets to remain viable in the United States.

Administrative Governance: Business Oregon and the Department of Revenue

The administration of the semiconductor R&D credit is unique among Oregon tax incentives because it requires joint oversight from two distinct state agencies: the Oregon Business Development Department (Business Oregon) and the Oregon Department of Revenue (DOR). This dual-track system ensures that only companies with legitimate ties to the semiconductor industry receive certification, while the DOR maintains its traditional role of auditing the financial and technical validity of the research claims.

Business Oregon Certification Process (OAR 123-401)

Before a taxpayer can claim the credit on their state tax return, they must obtain annual certification from Business Oregon. The administrative rules under Division 401 of Chapter 123 specify that the applicant must demonstrate they are a “qualified semiconductor company”. This definition is narrow and requires the entity to be primarily involved in the design, fabrication, assembly, testing, packaging, or validation of semiconductors, or the creation of specialized equipment and software for that industry.

The application for certification must be filed annually by October 15. During this process, the taxpayer must provide a detailed narrative describing how their research activities support their semiconductor business. This is the critical stage where the “permitted purpose” must be clearly articulated. Business Oregon evaluates these narratives to ensure the research is not merely peripheral to the semiconductor trade. Because the state has established an annual cap on the total amount of credits available—$35 million for 2024 and $38.25 million for 2025—the certification process also serves as a gatekeeping mechanism to manage the state’s fiscal exposure.

Department of Revenue Oversight (OAR 150-315-0195)

While Business Oregon certifies the company, the Department of Revenue governs the actual calculation and reporting of the credit. The DOR rules under OAR 150-315-0195 dictate that the credit must be calculated in accordance with IRC § 41, but only for research conducted within Oregon. The DOR also manages the refundability aspects of the credit, which vary based on the number of Oregon employees.

The DOR provides guidance on the specific forms required, primarily the Schedule OR-RESEARCH (Form 150-102-130), which replaces federal Form 6765 for state purposes. The DOR’s audit manual and technical bulletins emphasize that the taxpayer bears the burden of proving that their research meets the four-part test, including the permitted purpose. The department has the authority to request detailed project logs and time-tracking data to verify that the claimed expenses—such as wages for engineers or costs of wafer lots—were actually dedicated to a qualified functional improvement.

Functional Requirements of the Permitted Purpose Test

The permitted purpose test is effectively a functional mandate. For a research project to qualify, it must be intended to achieve a specific technical advancement in one of the following areas: functionality, performance, reliability, or quality. In the semiconductor domain, these criteria translate into concrete engineering goals that address the physical and electronic limitations of integrated circuits and their manufacturing processes.

Functionality and Performance

In semiconductor design, functionality relates to the introduction of new capabilities to a chip, such as adding a new instruction set to a microprocessor or integrating a new type of sensor into a micro-electromechanical system (MEMS). Performance, meanwhile, typically involves improvements in processing speed, clock frequency, or power efficiency. A project aimed at shrinking the gate length in a transistor to allow for more operations per second at a lower voltage satisfies both the functionality and performance aspects of the permitted purpose test.

Reliability and Quality

Reliability research in semiconductors focuses on the durability and longevity of the component. This might involve testing new substrate materials to prevent electromigration or developing advanced packaging techniques to protect chips from environmental stressors like heat and vibration. Quality, in the context of fabrication, often pertains to yield improvement. A research effort to refine a chemical-mechanical planarization (CMP) process to reduce surface defects on a wafer is a permitted purpose because it directly improves the quality and consistency of the final product.

The permitted purpose test is “project-based,” meaning each business component must be evaluated separately. If a company is developing a new server-side CPU, the research must be aimed at making that specific CPU more functional, performant, reliable, or of higher quality. General research that is not tied to a specific business component is typically excluded from the credit.

Excluded Activities and the Aesthetic Barrier

One of the most critical aspects of the permitted purpose requirement is the “negative definition”—what the test specifically excludes. Both federal and Oregon guidance are clear that certain activities, while they may involve significant cost and effort, do not meet the functional threshold for R&D tax credits.

Aesthetics and Cosmetic Changes

Any activity that is primarily focused on the style, taste, cosmetic design, or seasonal appearance of a product is disqualified. While this is a common issue in the consumer products industry, it also applies to technical sectors. For instance, if a semiconductor manufacturer changes the color of its cleanroom suits or the external housing of its etching machines for branding purposes, those costs are non-qualifying. The improvement must be intrinsic to the technical operation of the component.

Routine Customization and Adaptation

IRC § 41(d)(4)(B) excludes the “adaptation of an existing business component to a particular customer’s requirement or need”. In the semiconductor world, this frequently occurs when a design house takes an existing chip architecture and makes minor modifications to fit the pin configuration or interface requirements of a specific client. If these modifications do not involve the resolution of technical uncertainty—that is, if they rely on routine engineering principles where the outcome is predictable—they fail the permitted purpose test.

Post-Production and Maintenance

The research credit is intended to incentivize “upstream” innovation. Once a product has reached the stage of commercial production and is ready for sale, activities related to its production, distribution, or maintenance are generally excluded. However, if a technical uncertainty arises after production has begun—such as an unexpected failure rate in the field that requires a return to the experimental lab—the activities taken to resolve that uncertainty may regain eligibility.

Financial Mechanics: Rates, Calculations, and Refundability

The Oregon Semiconductor R&D Tax Credit is designed to be one of the most generous in the nation, but its calculation is subject to strict mathematical constraints and administrative caps.

The 15 Percent Credit Rate

The credit is calculated as 15 percent of the “excess” qualified research expenses. The term “excess” refers to the amount of QREs in the current year that exceed a historical base amount. The base amount is intended to ensure that the credit only rewards increases in innovation rather than subsidizing baseline spending.

For companies using the Regular Method, the base amount is calculated as:

Base Amount = Fixed-Base Percentage × Average Annual Oregon Gross Receipts (Prior 4 Years)

However, the base amount can never be less than 50 percent of the current year’s QREs. This effectively limits the maximum possible credit to 7.5 percent of total QREs in a given year (15% × 50%).

Alternative Simplified Credit (ASC) Method

Recognizing that many companies may lack the decades of historical data required for the regular method, Oregon (following IRC § 41(c)(4)) allows for the ASC method. Under the ASC, the credit is 14 percent of the amount by which current year QREs exceed 50 percent of the average QREs from the prior three years. If a company has no prior QREs, the ASC rate is 6 percent of current year QREs.

Refundability Tiers (ORS 315.519)

Perhaps the most innovative feature of the Oregon credit is its tiered refundability. Because many semiconductor startups and design firms operate for years without making a profit (and thus have no tax liability to offset), the state allows a portion of the credit to be issued as a cash refund. The percentage of the credit that is refundable depends on the company’s Oregon employee headcount at the end of the tax year.

This refundability structure is a powerful economic development tool, as it provides immediate liquidity to smaller, high-growth companies that are the most likely to be engaged in disruptive R&D.

Documentation and Substantiation Standards

The Department of Revenue’s audit procedures for the R&D credit are rigorous. Because the credit represents a direct “dollar-for-dollar” reduction in tax liability (or a cash refund), the state demands a high level of contemporaneous documentation to support every dollar claimed.

Technical Narratives and Project Lists

Taxpayers are expected to maintain a list of all research projects claimed and a technical narrative for each. This narrative must explicitly address the four-part test:

1. Permitted Purpose: What functional improvement was sought?
2. Elimination of Uncertainty: What technical unknown was being addressed?
3. Process of Experimentation: What alternatives were tested, and how?
4. Technological in Nature: What scientific principles were used?

Time Tracking and Expense Nexus

A common pitfall in R&D audits is the “nexus” between the expense and the research. It is not enough to say that an employee is an “engineer” and thus their entire salary qualifies. The taxpayer must show the specific amount of time each employee spent on “qualified services,” which includes direct research, direct supervision, and direct support.

Similarly, for supplies, the taxpayer must demonstrate that the materials were “consumed” in the experimentation process. In the semiconductor fab environment, this might include specialized gases, photoresists, and experimental wafers that are used during a trial run and cannot be sold to customers.

The 80 Percent “Substantially All” Rule

Under IRC § 41(d)(1)(C), “substantially all” of the research activities for a given business component must constitute a process of experimentation for a permitted purpose. The IRS and the Oregon DOR interpret “substantially all” to mean at least 80 percent, measured by cost or labor hours. If an auditor determines that more than 20 percent of the effort for a project was dedicated to non-qualifying activities (such as routine testing or aesthetic design), the entire project may be disqualified.

Comprehensive Example: Semiconductor Process Innovation

To illustrate the application of these principles, consider the following detailed scenario involving an Oregon-based company, Silicon Grove Innovations (SGI).

The Project: Extreme Ultraviolet (EUV) Resist Optimization

SGI is a qualified semiconductor company that develops advanced chemicals used in the lithography phase of chip fabrication. In 2024, they launched a project to develop a new “metal-oxide resist” specifically designed for EUV lithography at the 2nm process node.

Satisfying the Permitted Purpose

The project’s objective was to increase the “Performance” and “Quality” of the lithography process. Specifically, the goal was to reduce the “line-edge roughness” (LER) of the circuits printed on the wafer, which is a major technical barrier at the 2nm scale. By reducing LER, SGI hoped to improve the signal-to-noise ratio and overall reliability of the finished chips. This clearly constitutes a permitted purpose under the functional test.

Addressing Technical Uncertainty

At the start of the project, SGI’s chemists did not know the optimal ratio of tin-oxide nanoparticles to organic binders that would allow for high sensitivity to EUV light without sacrificing the structural integrity of the resist during the etching phase. This represents a significant technical uncertainty regarding the appropriate “method and design” of the business component.

Process of Experimentation

SGI’s research team formulated twelve different variations of the resist (the business component). They conducted a series of “wafer trials” where each formulation was applied to a test wafer and exposed to EUV light. They then used scanning electron microscopy (SEM) to measure the LER and cross-sectional stability of the patterns. This systematic “trial-and-error” process, backed by physical science principles (chemistry and physics), fulfills the experimentation and technological nature requirements.

Expenditure Identification and Calculation

For this project, SGI incurred the following Oregon-based expenses:

• Wages: $800,000 for five PhD chemists and three lab technicians directly performing the experiments.
• Supplies: $150,000 for high-purity chemicals and 100 test wafers consumed during the trials.
• Contract Research: $100,000 paid to an Oregon university to use their specialized EUV exposure tool. The qualified amount is $65,000 (65%).
• Total QREs for Project: $1,015,000.

SGI is a startup with 45 employees. Assuming SGI uses the ASC method and had an average QRE of $400,000 over the prior three years:

1. Current QRE: $1,015,000
2. ASC Base ($50% × $400,000): $200,000
3. Excess QRE: $815,000
4. Credit (14% × $815,000): $114,100

Because SGI has fewer than 150 employees, 75 percent of this credit ($85,575) is refundable if they have no tax liability.

Strategic Implications of the Statewide Cap

A significant, though often overlooked, aspect of the Oregon semiconductor R&D credit is the statewide annual cap. Unlike the federal credit, which is an “entitlement” for all who qualify, the Oregon credit is limited by the total amount of funding authorized by the legislature for each biennium.

For the 2024-2025 period, the budget was approximately $80 million. If the total “potential” tax credits from all certified applications exceed the annual cap (e.g., $35 million in 2024), Business Oregon must reduce the certified credit amounts. The administrative rules under OAR 123-401-0500 specify that the department will reduce certified amounts exceeding $200,000 by a ratio necessary to keep the total within the budget. This means that while a company may technically qualify for a $4 million credit based on their spending, their “certified” amount—and thus the amount they can legally claim on their tax return—may be significantly less if the program is oversubscribed.

This cap introduces a level of uncertainty into the financial planning of semiconductor firms. It places a premium on early registration (the one-time December 1, 2023 deadline for the 2024 tax year) and accurate annual certification filings. Companies must be prepared to demonstrate not just that they met the permitted purpose, but that they did so with a degree of technical rigor that justifies their place within the capped pool of state incentives.

The Future Outlook: 2024–2029

The Oregon Semiconductor Research and Development Tax Credit is currently scheduled to sunset on December 31, 2029. This five-year window is designed to coincide with the most intensive period of investment under the federal CHIPS Act. During this time, the state’s focus will likely remain on the “Permitted Purpose” as a means of ensuring that only high-value, functionally transformative research is subsidized.

There are ongoing discussions within the Oregon legislative and professional services communities regarding the potential for “modernizing” the state’s R&D tax code even further. This includes potential adjustments to how the state conforms to the capitalization and amortization requirements of IRC § 174. As of 2025, the “One Big Beautiful Bill Act” (OBBBA) at the federal level has proposed allowing immediate expensing for domestic R&D, and should this pass, Oregon may need to update its own administrative rules to remain in conformity.

For the professional peer, the key takeaway is that the “Permitted Purpose” is not a static definition but a functional mandate that requires constant technical justification. In the semiconductor industry, where the line between “process development” and “production” is often blurred, the ability to articulate the functional improvement sought by a project is the difference between a successful tax credit claim and a costly audit disallowance. Success in claiming the Oregon semiconductor R&D credit requires a holistic approach that integrates legal, financial, and engineering expertise to prove that every dollar spent was a dollar invested in the future of silicon technology.