Michigan Patent of the Month – February 2026

Introduction: The Selection of U.S. Patent No. 12,535,851

The global landscape of intellectual property is a chaotic and rapidly expanding frontier, particularly within the semiconductor sector where the cadence of innovation is measured in nanometers and gigahertz. Amidst this dense thicket of technological filings, specific inventions occasionally emerge that promise to fundamentally alter the trajectory of an industry. It is in this context that we announce the selection for the Michigan Patent of the Month for February 2026. The award has been bestowed upon U.S. Patent No. 12,535,851. Titled “Digital System Synchronization,” this seminal document was applied for on June 20, 2024, and officially granted by the United States Patent and Trademark Office (USPTO) on January 27, 2026. The patent is assigned to Movellus Circuits Inc., a pioneering semiconductor intellectual property firm with deep roots in the Michigan technology ecosystem.

The selection of this specific patent was not an arbitrary decision; it was the result of an exhaustive, rigorous evaluation process utilizing advanced Artificial Intelligence (AI) algorithms. This AI-driven methodology scanned, parsed, and analyzed over 1,000 potential patent candidates granted within the relevant cycle, filtering for indicators of novelty, technical robustness, and commercial viability. U.S. Patent No. 12,535,851 emerged from this competitive field of 1,000 candidates as the clear victor, securing its status as the premier intellectual property achievement for the state of Michigan this month.

The primary driver behind the selection of Patent 12,535,851 for the Michigan Patent of the Month award was its profound and immediate real-world impact. While many patents represent theoretical advancements or incremental improvements to existing widgets, this invention addresses a critical, systemic bottleneck in the “Angstrom Era” of semiconductor manufacturing: the “Clocking Wall.” As integrated circuits (ICs) scale down to 3nm and beyond, the physical limitations of distributing timing signals (clocks) via traditional analog means have become a primary inhibitor of performance and yield. The AI evaluation system flagged this patent because it offers a solution that is not merely an optimization, but a paradigm shift—moving from rigid, analog-heavy clocking architectures to flexible, intelligent, and fully synthesizable digital systems. The selection committee noted that this technology is foundational to the next generation of Artificial Intelligence (AI) hardware, autonomous automotive systems, and aerospace computing, making it a critical asset not just for Movellus, but for the broader U.S. semiconductor supply chain. By solving the physics-based challenges of jitter, voltage droop, and process variability through digital logic rather than analog tuning, Patent 12,535,851 demonstrates the high degree of “utility” and “non-obviousness” that the patent system—and the Michigan Patent of the Month award—is designed to honor.

Competitive Benchmarking and Technological Superiority

To fully appreciate the superiority of U.S. Patent No. 12,535,851, it is necessary to benchmark it against the incumbent technologies that have dominated the industry for decades. The primary competitor to the “Digital System Synchronization” described in the patent is the traditional Analog Phase-Locked Loop (PLL) and the associated analog clock tree distribution networks.

For the past forty years, the semiconductor industry has relied on Analog PLLs to generate the “heartbeat” of microchips. These circuits use voltage-controlled oscillators (VCOs), charge pumps, and loop filters composed of resistors and capacitors to maintain timing. While this technology was sufficient for larger process nodes (e.g., 28nm, 14nm), it faces severe limitations at advanced nodes (5nm, 3nm, 2nm). The invention described in Patent 12,535,851 dismantles these limitations by implementing synchronization entirely in the digital domain.

Comparative Analysis: Digital vs. Analog Architecture

The following analysis details the specific technical vectors where U.S. Patent No. 12,535,851 demonstrates objective superiority over legacy analog competitors.

Table 1: Competitive Benchmarking of Clocking Architectures

Why the Patent’s Technology is Superior

The superiority of the technology described in Patent 12,535,851 stems from its alignment with the fundamental physics of modern lithography.

Solving the “Analog Scaling Lag”

The most significant competitive advantage is the “synthesizable” nature of the invention. Competitors offering analog PLLs (such as those from legacy IP providers) provide “hard macros”—fixed physical layouts. As the industry moves to 3nm and 2nm, transistors shrink, but analog components (like the loop filter capacitor) do not shrink at the same rate. This means that with every generation, the analog PLL occupies a larger percentage of the total chip area, becoming a “tax” on the design. Movellus’s patent describes a system that utilizes digital logic gates to perform the synchronization. Because digital gates shrink perfectly in accordance with Moore’s Law, the Movellus solution becomes more efficient with every new generation of manufacturing technology. This allows chip designers to reclaim square millimeters of silicon area—which translates to millions of dollars in cost savings per wafer—and use that space for additional revenue-generating features, such as more AI tensor cores or larger cache memory.

Deterministic Jitter Management

In the analog world, “jitter” (the deviation of the clock edge from its ideal time) is a probabilistic phenomenon often caused by thermal noise and power supply fluctuations. It is difficult to predict and harder to control. The digital architecture outlined in Patent 12,535,851 treats time as a digital variable. By using digital-to-time converters (DTCs) and time-to-digital converters (TDCs), the system can measure and correct timing errors with mathematical precision. This results in “Intelligent Clock Networks” that can dynamically compensate for voltage droops in real-time. For example, if a massive AI workload causes the chip’s voltage to dip (droop), an analog PLL might lose its lock or introduce fatal jitter. The Movellus digital system can detect this droop and instantaneously adjust the clock frequency to maintain stability, preventing a system crash. This “droop response” capability is a distinct competitive advantage over passive analog competitors.

Acceleration of Time-to-Market

In the semiconductor industry, being first to market can determine the success or failure of a product line. Converting an analog IP block from a 5nm process to a 3nm process is a manual, labor-intensive task that can take specialized analog engineers six months or more. The technology in Patent 12,535,851 is “fully synthesizable,” meaning it exists as software code (RTL). It can be ported to a new process node in a matter of weeks, utilizing standard automated tools. This agility allows companies using Movellus IP to launch their products months ahead of competitors who are stuck redesigning their legacy analog clocking circuits.

Real-World Impact and Future Potential

The “Michigan Patent of the Month” award is not given for theoretical elegance alone; it requires evidence of tangible impact. U.S. Patent No. 12,535,851 is currently influencing the design of the world’s most advanced computing systems and holds the potential to unlock entirely new categories of electronic devices.

Current Real-World Impact

Enabling the Generative AI Infrastructure

The most immediate impact of this patent is visible in the data centers powering Generative AI (GenAI) models like GPT-4, Gemini, and Claude. These models are trained on massive clusters of GPUs and AI accelerators, often numbering in the tens of thousands.

• The Problem: AI workloads are characterized by “bursty” activity. When a neural network layer activates, billions of transistors switch simultaneously, causing massive spikes in current demand (high di/dt). This creates severe voltage noise on the power supply rails. Traditional analog PLLs are highly sensitive to this noise; their output frequency jitters, which limits the maximum speed at which the AI chip can run.
• The Solution: The Digital System Synchronization technology is inherently robust to this supply noise because it operates using the same digital logic levels as the AI cores themselves. Furthermore, its ability to dynamically detect and respond to voltage droop allows these AI chips to run at higher frequencies with lower safety margins. This directly translates to faster training times for AI models and lower energy costs for data center operators—a multi-billion dollar impact on the global AI economy.

Automotive Safety and “The Software-Defined Vehicle”

Michigan is the automotive capital of the world, and this patent reinforces that status in the digital age. Modern vehicles are evolving into “software-defined vehicles” heavily reliant on high-performance System-on-Chips (SoCs) for Autonomous Driving (ADAS) and infotainment.

• The Problem: Automotive chips must operate for 15+ years in harsh environments (extreme heat, vibration). Analog circuits suffer from “aging”—their characteristics drift over time, potentially leading to failure. In a safety-critical system like an autonomous braking controller, a clock failure can be catastrophic.
• The Solution: The digital circuits described in Patent 12,535,851 are far more resilient to aging and temperature variations than analog components. They provide the extreme reliability required for ISO 26262 functional safety compliance. Additionally, the small footprint allows for redundancy (using two clocks instead of one) without blowing up the chip size, further enhancing safety.

Supply Chain Resilience

The post-pandemic era highlighted the fragility of the semiconductor supply chain. When a specific foundry line (e.g., at TSMC or Samsung) becomes overbooked, chip companies need to move their designs to a different factory.

• The Impact: Because the Movellus digital synchronization technology is synthesizable code, it allows chip companies to move their designs between foundries with minimal friction. This “portability” provides strategic resilience to the U.S. electronics industry, allowing it to adapt to geopolitical or logistical disruptions.

Future Potentials

The “Angstrom” Era (2nm and Beyond)

As the industry roadmap extends to 2nm (20A) and 1.4nm (14A) processes, the voltage headroom available for circuits will drop to near 0.6V. At these ultra-low voltages, traditional analog circuits essentially stop working—they cannot turn on the transistors reliably. The digital architecture of Patent 12,535,851 is uniquely positioned to function in this “near-threshold” regime. It is likely that within the next decade, analog PLLs will be completely phased out of advanced digital processors in favor of the all-digital approach pioneered by this patent.

Chiplet Integration and Die-to-Die Connectivity

The future of high-performance computing is not single massive chips, but “chiplets”—multiple smaller silicon dies stitched together in a single package.

• The Potential: Synchronizing data transfer between these separate chiplets is an immense challenge. The “phase-aligned relationship” capabilities described in Patent 12,535,851 are perfectly suited for this application. We anticipate this technology will become a standard for “Die-to-Die” (D2D) interfaces, enabling the massive supercomputer-on-a-chip designs required for future scientific research and climate modeling.

Aerospace and Radiation Hardening

As humanity pushes further into space, electronics must survive the high-radiation environment outside Earth’s magnetosphere. Analog circuits are prone to “Single Event Transients” (SETs) where a cosmic ray strike causes a glitch. Digital logic, however, can be designed with “Triple Modular Redundancy” (voting logic) to ignore these errors. The all-digital nature of the Movellus patent makes it an ideal candidate for radiation-hardened applications, including deep-space probes and commercial satellite constellations.

R&D Tax Credit Analysis: The 4-Part Test and Swanson Reed’s Role

The development of a breakthrough technology like U.S. Patent No. 12,535,851 represents a massive investment of capital and intellectual effort. For companies engaged in similar high-stakes innovation, the Research & Development (R&D) Tax Credit (under Internal Revenue Code Section 41) is a vital mechanism to recoup costs and fuel further growth. However, eligibility is not automatic; it requires strict adherence to the IRS “Four-Part Test.”

The following section provides a detailed analysis of how a project utilizing the technology in Patent 12,535,851 would meet the Four-Part Test, and how Swanson Reed, a specialist R&D tax advisory firm, assists companies in substantiating such claims.

The Four-Part Test Applied to Digital Clocking Innovation

To qualify as “Qualified Research Activities” (QRA), the development work must satisfy all four of the following criteria.

Part 1: Permitted Purpose

Definition: The activity must relate to a new or improved business component’s function, performance, reliability, or quality. The research cannot be for purely aesthetic purposes or for routine maintenance. Application to Patent 12,535,851: The development of “Digital System Synchronization” clearly satisfies this test. The purpose of the project is to create a new business component (the synthesizable clocking IP core) with improved performance (lower jitter, higher frequency), reliability (better aging characteristics), and efficiency (smaller area, lower power).

• Qualifying Example: Engineering efforts to redesign the clock distribution architecture to achieve a 50% reduction in power consumption while maintaining phase lock.
• Non-Qualifying Example: Changing the color of the GUI in the software used to demo the chip, or routine bug fixes on a legacy analog PLL that do not improve its underlying functionality.

Part 2: Technological in Nature

Definition: The activity must fundamentally rely on principles of the “hard sciences”—physical or biological sciences, engineering, or computer science.

Application to Patent 12,535,851:

The innovation described in the patent is deeply rooted in Electrical Engineering, Computer Engineering, and Semiconductor Physics.

• Evidence: The patent discusses “transmit circuitry,” “clocked-device circuitry,” and “phase-aligned relationships”. Developing these requires the application of Ohm’s Law, transmission line theory, and digital logic design. The engineers would rely on complex simulation tools (like SPICE for analog effects and Verilog for digital logic) to model the behavior of electrons and signals at the nanometer scale. This is the antithesis of “soft” research (like market research or social sciences), firmly grounding the work in the hard sciences required by the IRS.

Part 3: Elimination of Uncertainty

Definition: At the outset of the project, there must be uncertainty regarding the capability to develop the component, the method of development, or the appropriate design of the component.

Application to Patent 12,535,851:

In developing a novel all-digital PLL for a 3nm process, significant technical uncertainty exists.

• Uncertainty of Capability: “Can we achieve sub-picosecond jitter performance using only digital gates, which are inherently noisy?”
• Uncertainty of Design: “What is the optimal architecture for the ‘multiple transmitters’ mentioned in the patent? Should they be distributed in a mesh or a star topology to minimize skew?”
• Uncertainty of Method: “How do we compensate for the non-linear capacitance of 3nm FinFET transistors during a voltage droop event?”
  The mere fact that this technology was patentable (i.e., novel and non-obvious) is strong evidence that these uncertainties existed and were not easily solvable by standard industry knowledge. The project required the discovery of information that was not known at the start.

Part 4: Process of Experimentation

Definition: Substantially all (at least 80%) of the activities must constitute a process of experimentation designed to evaluate one or more alternatives to achieve a result. This involves simulation, systematic trial and error, or modeling. Application to Patent 12,535,851: This is the most critical and documentation-heavy requirement. A project developing this patent would inevitably involve a cyclical process of hypothesis, testing, and refinement.

1. Hypothesis: The engineering team hypothesizes that a new “Gain Normalization” algorithm will stabilize the clock during high-voltage droop events.
2. Simulation (Testing): They code the algorithm in RTL and run Monte Carlo simulations across thousands of “Process, Voltage, and Temperature” (PVT) corners to stress-test the design.
3. Analysis: The simulation reveals that the clock loses lock at -40°C. The hypothesis is proven incomplete.
4. Refinement (Iteration): The team modifies the algorithm to include a temperature-compensation coefficient and re-runs the simulations.
5. Alternatives: They evaluate different architectures for the Time-to-Digital Converter (TDC)—comparing a “Vernier Delay Line” vs. a “Flash TDC”—and select the one that offers the best trade-off between power and accuracy.
   This systematic evaluation of alternatives is the hallmark of qualified R&D.

How Swanson Reed Helps Claim the Credit

Claiming the R&D tax credit for complex semiconductor IP is fraught with audit risk if not documented correctly. The IRS frequently scrutinizes software and engineering claims, looking for “routine” work labeled as R&D. Swanson Reed, as a specialist firm, employs a distinct, multi-layered methodology to ensure compliance and maximize the claim value.

The Mandatory “6-Eye Review” Process

Swanson Reed distinguishes itself with a rigorous internal quality control process known as the “6-Eye Review”. Every R&D claim is reviewed by three distinct sets of experts before it is filed:

1. Eye Pair 1 (Qualified Engineer/Scientist): A domain expert (e.g., a former semiconductor engineer) reviews the technical narrative. They understand the difference between “routine place-and-route” (non-qualified) and “architectural experimentation” (qualified). They ensure the technical description of the “Digital System Synchronization” accurately reflects the “Process of Experimentation” and uses the correct industry terminology.
2. Eye Pair 2 (Tax Attorney/Specialist): This legal expert reviews the claim for eligibility under current case law. They ensure that the “uncertainties” claimed are valid under precedents like Sudderth or Union Carbide. They also verify that the research was not “funded” by a client in a way that would disqualify it (checking contract terms for financial risk and rights retention).
3. Eye Pair 3 (CPA/Enrolled Agent): The financial expert reviews the calculation of Qualified Research Expenses (QREs). They ensure that wages are allocated correctly based on the percentage of time spent on R&D, and that supply costs (like cloud compute time for simulations or MPW shuttle runs) are properly substantiated.

AI-Powered Documentation with TaxTrex

Contemporaneous documentation—records created while the work is happening—is the gold standard for IRS audits. Swanson Reed utilizes TaxTrex, a proprietary AI-driven platform, to automate this process.

• Real-Time Tracking: TaxTrex integrates with the engineers’ workflow to track project progress. For the Movellus patent, it would have prompted the engineers in 2024 to log their “failed experiments” and “design iterations” as they occurred, creating a time-stamped audit trail.
• Compliance Insights: The AI analyzes the project descriptions and flags potential risks. If an engineer describes a task as “bug fixing,” TaxTrex might prompt for clarification: “Did this bug fix require resolving a technical uncertainty regarding the system architecture?” This ensures the language used aligns with the tax code.

Audit Defense with CreditARMOR

Given the high dollar value of R&D credits in the semiconductor industry, audits are a possibility. Swanson Reed’s CreditARMOR product provides a shield against this risk.

• It includes a pre-filing audit readiness assessment.
• In the event of an IRS examination, CreditARMOR covers the cost of defense, providing the CPAs, attorneys, and technical specialists needed to defend the claim.
• For a patent-based claim like Patent 12,535,851, Swanson Reed would utilize the patent application history and the “6-Eye” technical reports to definitively prove that the work met the “Technological in Nature” and “Elimination of Uncertainty” tests.

Final Thoughts

The selection of U.S. Patent No. 12,535,851 as the Michigan Patent of the Month for February 2026 is a testament to the vitality and strategic importance of the Michigan technology sector. By successfully reimagining the fundamental physics of clock distribution—transitioning from the limitations of analog circuitry to the scalability of digital intelligence—Movellus Circuits Inc. has delivered an invention with profound real-world impact.

This patent does not merely solve a technical problem; it unlocks the future of the Artificial Intelligence economy. It enables the creation of larger, faster, and more energy-efficient AI accelerators that are critical for training the next generation of Large Language Models. It enhances the safety and reliability of autonomous vehicles, a cornerstone of Michigan’s industrial future. And it provides the aerospace industry with the robust, radiation-hardened components needed for the new space age.

Furthermore, the rigorous, scientific process required to bring this invention to life serves as a definitive example of “Qualified Research” under the U.S. tax code. Through the disciplined application of the Four-Part Test—validating the Purpose, Technology, Uncertainty, and Experimentation—innovators can leverage the R&D Tax Credit to fuel their continued growth. With the support of specialized advisory frameworks like Swanson Reed’s 6-Eye Review and TaxTrex technology, companies can secure the capital needed to transform today’s patents into tomorrow’s ubiquitous technologies. As we move through February 2026, U.S. Patent No. 12,535,851 stands as a beacon of American innovation, signaling that the future of computing will be digital, intelligent, and synchronized.

Swanson Reed Michigan Office: 847 Sumpter Road, Belleville, Michigan. Specialists in R&D Tax Credit substantiation for the semiconductor, automotive, and high-tech industries.