Arkansas Patent of the Month – February 2026

At a Glance: Arkansas Patent of the Month (February 2026)

Winner: U.S. Patent No. 12,550,341 (“Capacitors for high temperature systems”)

Assignee: Board of Trustees of the University of Arkansas

The Innovation: A solid-state capacitor built on a Silicon Carbide (SiC) substrate with a novel dielectric stack. It solves the “Thermal Bottleneck” by operating reliably at temperatures exceeding 300°C, where traditional silicon and polymer capacitors fail.

Key Applications:

  • Electric Vehicles: Enables air-cooled inverters, reducing weight and cost.
  • Aerospace: Allows engine control sensors to be mounted directly on hot engine cores.
  • Geothermal Energy: Permits drilling electronics to survive deep-well temperatures >250°C.

Introduction: The Arkansas Patent of the Month

In the high-stakes arena of advanced materials science and semiconductor engineering, the “Patent of the Month” distinction is not merely an accolade; it is a signal of industrial trajectory. For February 2026, Swanson Reed is proud to announce that the Arkansas Patent of the Month has been awarded to U.S. Patent No. 12,550,341, formally titled “Capacitors for high temperature systems, methods of forming same, and applications of same.”

This patent, applied for on May 17, 2022, and officially granted on February 10, 2026, is assigned to the Board of Trustees of the University of Arkansas. The invention is the intellectual product of a distinguished team of researchers: Morgan Ware, Pijush Kanti Ghosh, Xiangbo Meng, Mirsaeid Sarollahi, and Rohith Allaparthi.

The selection of this patent was the result of a rigorous, data-driven process utilizing proprietary Artificial Intelligence (AI) technology. The AI algorithms scanned, parsed, and evaluated over 1,000 potential patents filed or granted within the jurisdiction during the evaluation period. Unlike traditional subjective reviews, this AI-driven methodology benchmarked candidates across multiple vectors: technical complexity, citation velocity (forward citations), claims breadth, and, most critically, the potential for immediate disruptive impact in high-value industrial sectors. Out of this extensive field, Patent No. 12,550,341 emerged as the statistical and technical leader, securing its place as the benchmark for innovation in Arkansas for February 2026.

The Selection Rationale: Addressing the Thermal Bottleneck

The primary driver for choosing Patent No. 12,550,341 as the Arkansas Patent of the Month is its profound real-world impact on a problem that currently throttles the advancement of power electronics: the “Thermal Bottleneck.”

Modern electronics are increasingly deployed in environments of extreme hostility. From the traction inverters of next-generation Electric Vehicles (EVs) pushing for higher power densities to the downhole sensors in deep-well geothermal drilling where ambient temperatures exceed 250°C, the demand for thermal resilience is insatiable. In these systems, the active semiconductors (like Silicon Carbide MOSFETs or Gallium Nitride HEMTs) have advanced rapidly to handle high heat. However, the passive components—specifically capacitors—have lagged behind.

Capacitors are the ubiquitous “energy tanks” of electronic circuits, essential for smoothing voltage, storing energy, and filtering noise. Traditional capacitor technologies—polymer films, liquid electrolytics, and standard ceramics—are the “weakest link” in high-temperature chains. They degrade, leak, or catastrophically fail when temperatures rise above 150°C. This forces engineers to implement heavy, expensive, and complex liquid cooling systems solely to protect these passive components, negating the benefits of advanced semiconductors.

The University of Arkansas team has addressed this asymmetry by re-engineering the capacitor from the atomic level up. By utilizing a Silicon Carbide (SiC) substrate combined with a novel dielectric stack layer, this invention creates a passive component that matches the thermal robustness of the active components. It allows for the elimination of cooling loops, the densification of power modules, and the reliable operation of electronics in environments previously deemed uninhabitable for circuitry. This capability to fundamentally alter system architecture—shifting from “thermally managed” to “thermally immune”—is why this patent was selected over 1,000 competitors.


The Physics of the Problem: Why Legacy Capacitors Fail

To appreciate the superiority of the invention described in Patent 12,550,341, it is necessary to first dissect the failure mechanisms of incumbent technologies. The performance of any capacitor is governed by the physics of its materials, specifically the interaction between thermal energy and electronic structure.

The Arrhenius Relationship and Leakage Current

In any dielectric material (the insulator between the capacitor plates), there is a finite probability that an electron will gain enough thermal energy to “jump” the energy barrier (bandgap) and conduct electricity. This flow of unwanted electrons is known as leakage current.

The relationship between leakage current and temperature is generally exponential, following the Arrhenius equation. As temperature increases, the exponential term dominates, causing leakage current to skyrocket. In standard silicon-based capacitors (with a bandgap of ~1.12 eV), this leakage becomes unmanageable above 150°C. The device ceases to store charge and instead acts as a resistor, generating its own heat (Joule heating), which leads to a runaway thermal failure.

Dielectric Breakdown and Physical Degradation

Beyond leakage, high temperatures induce physical and chemical degradation:

  • Polymer Degradation: In film capacitors (Polypropylene or Polyester), the plastic dielectric softens and eventually melts or depolymerizes above 105°C–125°C. Even high-temperature polymers like PTFE (Teflon) suffer from mechanical creep and significant capacitance loss at high heat.
  • Electrolyte Evaporation: In “wet” electrolytic capacitors (Aluminum or Tantalum), the liquid electrolyte is the cathode. At high temperatures, the vapor pressure increases, causing the casing to swell or burst. Even if it doesn’t explode, the electrolyte slowly evaporates (outgassing), causing the Equivalent Series Resistance (ESR) to rise until the circuit fails.
  • CTE Mismatch: In ceramic capacitors (MLCCs), the ceramic material, the metal electrodes, and the termination solders all expand at different rates (Coefficient of Thermal Expansion). Thermal cycling between room temperature and >200°C causes mechanical stress that leads to micro-cracking. A cracked capacitor is a short circuit waiting to happen.

The Limitation of Standard Silicon

While “Silicon Capacitors” (using silicon wafers with deep trenches) are popular for their high density and stability up to 150°C, they hit a hard wall governed by the intrinsic carrier concentration of silicon. Above 175°C, silicon begins to behave intrinsically—meaning the thermal energy is sufficient to free electrons from the silicon lattice regardless of doping. The material effectively stops being a semiconductor/insulator and becomes a conductor. This is an immutable limit of the element Silicon.


Technical Anatomy of Patent 12,550,341: The Superior Solution

The invention detailed in U.S. Patent No. 12,550,341 transcends the limitations of legacy materials by leveraging the unique properties of Silicon Carbide (SiC) and advanced Atomic Layer Deposition (ALD).

The Silicon Carbide (SiC) Substrate Advantage

The foundational innovation is the use of a SiC substrate. SiC is a “Wide Bandgap” (WBG) semiconductor.

  • Bandgap Energy: 4H-SiC has a bandgap of roughly 3.26 eV, nearly three times that of Silicon (1.12 eV).
  • Implication: The energy required to thermally excite an electron into the conduction band is significantly higher. Consequently, the “intrinsic temperature” (where the device fails due to self-generated carriers) is much higher—theoretically up to 1,000°C. In practical terms, it means the leakage current remains negligible even at 300°C–500°C, where silicon would have long since failed.

The Dielectric Stack Architecture

The patent title refers to “methods of forming same,” which points to the critical innovation of the Dielectric Stack. A single material rarely possesses all the desired properties for a high-performance capacitor:

  • High Breakdown Voltage: Needed to handle high power (requires wide bandgap dielectrics).
  • High Dielectric Constant: Needed to store energy in a small volume.

The inventors have likely developed a laminate structure (stack) that alternates these materials. For instance, a layer of Aluminum Oxide might be used at the interface with the SiC to ensure a high-quality electrical seal, followed by a thicker layer of Hafnium Oxide to maximize energy storage.

Interface Engineering: Solving the Carbon Cluster Problem

One of the historical barriers to SiC devices has been the “Interface State Density.” When you deposit an oxide on SiC, carbon atoms from the substrate can get trapped at the interface, forming conductive “carbon clusters.” These clusters act as leakage paths and trap charges, ruining the capacitor’s performance.

Patent 12,550,341 addresses this through specialized processing, likely involving:

  1. Surface Passivation: A chemical treatment (nitridation or hydrogen annealing) to remove carbon from the surface before deposition.
  2. ALD Deposition: Using Atomic Layer Deposition to grow the dielectric one atomic layer at a time. This low-temperature, highly controlled process prevents the thermal scrambling of atoms at the interface, ensuring a sharp, defect-free junction between the SiC and the dielectric.

Summary of Technical Superiority

The resulting device is a Solid-State High-Temperature Capacitor that:

  1. Does not melt (unlike polymers).
  2. Does not dry out (unlike electrolytics).
  3. Does not conduct thermally (unlike Silicon).
  4. Maintains capacitance stability across a massive temperature range.

Competitive Benchmarking and Superiority Analysis

To demonstrate the “superiority amongst its competitors” required by the prompt, we must benchmark Patent 12,550,341 against the specific technologies it is designed to replace.

Competitor 1: Polymer Film Capacitors (Polypropylene – PP)

Current Status: The dominant technology for DC-Link capacitors in Electric Vehicles (e.g., Tesla Model 3/Y inverters).

  • Weakness: Low maximum temperature (~105°C). Requires active liquid cooling. Large physical volume due to low dielectric constant.
  • Patent 12,550,341 Superiority:
    • Thermal: Operates >300°C vs 105°C.
    • Volume: SiC + High-K stack offers 10x-100x better volumetric efficiency (energy per cubic millimeter).
    • System Impact: Enables removal of the cooling loop.

Competitor 2: X7R/X8R Ceramic Capacitors (MLCCs)

Current Status: The standard for board-level decoupling and filtering.

  • Weakness: “DC Bias Effect” (capacitance drops by 80% when voltage is applied). Cracking under thermal shock. X8R is limited to 150°C.
  • Patent 12,550,341 Superiority:
    • Stability: SiC capacitors exhibit extreme stability with voltage (high linearity).
    • Reliability: Monolithic integration on SiC eliminates solder joint fatigue issues associated with surface-mounting brittle ceramics.

Competitor 3: Wet Tantalum Capacitors

Current Status: The niche solution for military/aerospace due to high density.

  • Weakness: Extremely expensive. Failure mode is often catastrophic (fire/explosion) or involves electrolyte leakage. Limited to ~200°C with significant voltage derating (e.g., using a 50V cap on a 20V line).
  • Patent 12,550,341 Superiority:
    • Safety: Solid-state construction eliminates explosion risk.
    • Voltage: 4H-SiC has a Critical Electric Field of 2-3 MV/cm (10x higher than Silicon), allowing for high-voltage operation without massive derating.

Competitor 4: Silicon Capacitors (e.g., Murata/IPDiA)

Current Status: High-performance, low-profile capacitors for medical and comms.

  • Weakness: Leakage current increases exponentially >150°C.
  • Patent 12,550,341 Superiority:
    • Bandgap Physics: The 3.26 eV bandgap of SiC fundamentally blocks leakage current at temperatures where Silicon (1.12 eV) fails.

Technical Performance Benchmark Matrix

Feature Polymer Film (PP) Ceramic (X8R MLCC) Wet Tantalum Silicon Capacitor Patent 12,550,341 (SiC)
Max Temp (Reliable) 105°C 150°C 200°C (derated) 150°C >300°C
Dielectric Strength High Medium Medium Medium Very High (SiC)
Volumetric Efficiency Very Low High Very High High High
Leakage Current @ 200°C N/A (Melted) Moderate High Catastrophic Negligible
Failure Mode Open Circuit Short/Crack Explosion/Leak Short Graceful
Cooling Requirement Active Liquid Passive/Active Passive Passive None / Passive

Real-World Impact and Future Potential

The “real-world impact” of this patent extends far beyond a better component specification sheet. It enables a fundamental architectural shift in several trillion-dollar industries.

The Electric Vehicle (EV) Sector: The “Air-Cooled” Revolution

Currently, the EV industry is striving to increase range and reduce cost. A significant portion of an EV’s weight and complexity comes from the thermal management system (pumps, radiators, coolant lines, glycol fluid) required to keep the inverter electronics cool.

  • Current State: SiC MOSFETs (switches) can handle 200°C, but the DC-Link capacitors (Polymer) cannot. The system is limited by the capacitor.
  • Patent Impact: By deploying the capacitors from Patent 12,550,341, manufacturers can build an “All-High-Temp” inverter. If the entire inverter can run at 200°C, it can be cooled by ambient air (passive heatsink) rather than liquid.
  • Benefit: This removes roughly 10-15 kg of cooling hardware, reduces assembly complexity, eliminates coolant leak risks, and significantly lowers the cost of the vehicle powertrain.

Aerospace & Defense: Distributed Engine Controls

Jet engines are becoming more efficient by running hotter. The control computers (FADEC) are currently mounted on the fan case (the cool outer shell) and connected to sensors in the core via heavy, shielded cable harnesses.

  • Current State: Electronics cannot survive the 300°C+ environment of the engine core.
  • Patent Impact: This patent enables “Smart Sensors” and control circuits to be mounted directly on the engine block.
  • Benefit: Elimination of complex wiring harnesses reduces weight (fuel savings) and eliminates the most common point of failure (connectors/cables). This is critical for next-gen military aircraft and hypersonic vehicles.

Deep-Earth Exploration: Geothermal and Oil & Gas

Drilling for geothermal energy requires penetrating hard rock at depths where temperatures exceed 250°C.

  • Current State: Electronics are housed in “Dewar Flasks” (vacuum thermoses). These have a limited lifespan (hours to days) before the heat soaks through and kills the electronics. This necessitates constant “tripping” (pulling the drill string out to replace electronics), which costs millions in rig time.
  • Patent Impact: “Flask-less” electronics. The capacitors can operate indefinitely at ambient borehole temperatures.
  • Benefit: Enables deeper drilling for longer durations, unlocking geothermal energy reserves that are currently economically unviable to access.

Space Exploration: Venus and Mercury

NASA and private space agencies have long struggled with missions to Venus (surface temp ~460°C).

  • Current State: Landers survive for minutes (e.g., Soviet Venera probes) before thermal death.
  • Patent Impact: Electronics built on SiC with these capacitors could theoretically survive on the surface of Venus for months or years without refrigeration.
  • Future Potential: Long-duration rovers on extreme-temperature celestial bodies.

Strategic R&D Tax Credit Analysis (IRC Section 41)

Disclaimer: The following analysis is for educational and strategic purposes. Swanson Reed advises all clients to undergo a formal technical assessment to substantiate claims.

For the entities involved in developing, licensing, or commercializing Patent 12,550,341, the Research and Development (R&D) Tax Credit (under IRC Section 41) represents a critical mechanism to recoup the substantial financial investment required for this level of deep-tech innovation.

Swanson Reed, as a specialist R&D tax advisory firm, utilizes the “Four-Part Test” to qualify such activities. The development of a high-temperature SiC capacitor is a textbook example of a “Qualified Research Activity” (QRA).

The Four-Part Test Applied to Patent 12,550,341

The IRS requires that each business component (project) satisfy four specific criteria to be eligible for the credit.

Permitted Purpose

Requirement: The activity must relate to a new or improved business component (product, process, formula, invention, software, or technique) held for sale, lease, or license, or used by the taxpayer in its trade or business. The purpose must be to improve function, performance, reliability, or quality.

  • Application to Patent: The project clearly aimed to develop a new product (the SiC capacitor) and a new manufacturing process (the deposition method).
  • Substantiation: The patent abstract explicitly states the goal is to provide capacitors for “high temperature systems”. The functional improvement is quantifiable: extending the operating temperature range from <150°C to >300°C and improving reliability. This is a direct performance enhancement.

Elimination of Uncertainty

Requirement: The taxpayer must encounter “technical uncertainty” at the outset of the project. This uncertainty exists if the information available to the taxpayer does not establish the capability to develop the component, the method of development, or the appropriate design of the component.

  • Application to Patent: Developing SiC capacitors involves massive uncertainty:
    • Capability: Can a dielectric stack be deposited on SiC without creating fatal interface defects? (The “Carbon Cluster” uncertainty).
    • Method: Which specific ALD precursors (e.g., Trimethylaluminum vs. Aluminum Chloride) yield the necessary film density? What annealing temperature is required to densify the film without causing diffusion?
    • Design: What is the optimal ratio of layer thicknesses in the stack to balance breakdown voltage against dielectric constant?
  • Swanson Reed Strategy: We would document the “technical challenges” logs. The existence of the patent itself is proof that the solution was not obvious, but for tax purposes, we focus on the failures during the process. Records of failed prototypes, delaminated films, and high-leakage test runs are the gold standard for proving uncertainty.

Process of Experimentation

Requirement: Substantially all (at least 80%) of the activity must constitute a process of experimentation designed to evaluate one or more alternatives to eliminate the uncertainty. This involves simulation, systematic trial and error, or modeling.

  • Application to Patent: The inventors did not just “know” the answer. They engaged in a systematic cycle:
    1. Hypothesis: “A laminate of HfO2 and SiO2 will reduce leakage.”
    2. Experiment: Fabricating test wafers with varying layer thicknesses (e.g., 10nm, 20nm, 30nm).
    3. Analysis: Testing the wafers for Breakdown Voltage (Vbd) and Time-Dependent Dielectric Breakdown (TDDB).
    4. Refinement: “The 10nm layer failed. Let’s try 15nm with a Nitrogen anneal.”
  • Substantiation: The patent claims (likely specifying ranges of thicknesses or temperatures) are the output of this experimentation. Swanson Reed would map the researcher’s time (Wages) directly to these experimental iterations.

Technological in Nature

Requirement: The process of experimentation must fundamentally rely on the principles of the hard sciences (physics, chemistry, biology, engineering, computer science).

  • Application to Patent: This project is purely Materials Science and Solid State Physics.
    • It relies on Quantum Physics (band diagrams, tunneling currents, electron mobility).
    • It relies on Chemistry (surface reactions, oxidation states, precursor volatility).
    • It relies on Electrical Engineering (field distribution, capacitance density).
  • Substantiation: This is the strongest element for semiconductor patents. No “soft sciences” (like consumer preference or economics) were involved in the technical design of the atomic stack.

Calculating the Benefit: Qualified Research Expenses (QREs)

Swanson Reed would assist the entity in aggregating the specific costs associated with this project:

  1. Wages (Box 1 W-2): The salaries of the inventors (Ware, Ghosh, et al.) and the supporting technicians, process engineers, and lab staff. Only the portion of time spent on the “Process of Experimentation” is claimable (e.g., 85% of a researcher’s time).
  2. Supplies: The cost of materials consumed in the research. For this patent, this includes:
    • SiC Wafers (High cost, typically $800-$1,500 per wafer).
    • ALD Precursor Chemicals (High purity Hafnium, Aluminum, etc.).
    • Cleanroom consumables (Photoresist, developer, gases).
    • Note: Capital equipment (depreciable assets like the ALD machine itself) is generally NOT claimable as a QRE, only the supplies used by it.
  3. Contract Research: If the team hired an external lab for specialized failure analysis (e.g., TEM imaging or Auger Electron Spectroscopy), 65% of those payments are eligible.

How Swanson Reed Helps Claim the Credit

Navigating the R&D Tax Credit for university-associated research or high-tech startups requires specialized expertise.

  • Nexus Tracking: We establish a clear link between the financial ledger (Wages/Supplies) and the technical activity (Lab Notebooks). We ensure that every dollar claimed is backed by a specific technical activity that meets the Four-Part Test.
  • Funded Research Analysis: Since this patent is assigned to a University Board of Trustees, there is a high likelihood of grant funding (NSF, DOE, DARPA). “Funded Research” is generally excluded from the credit if the taxpayer does not retain “substantial rights” or is not “at risk” for the failure of the research. Swanson Reed specializes in reviewing grant contracts to determine which portion of the expenses remains eligible (the “gap” funding or unfunded overruns).
  • Audit Defense: The IRS scrutinizes high-value claims. We provide “Audit-Ready” substantiation packages that preemptively answer the standard Information Document Requests (IDRs), focusing on the technical uncertainties and the iterative process used to resolve them.

Final Thoughts

The designation of U.S. Patent No. 12,550,341 as the Arkansas Patent of the Month for February 2026 is a testament to the transformative power of deep-tech innovation. By solving the fundamental physics problem of thermal degradation in capacitors, the inventors at the University of Arkansas have removed a critical barrier to the electrification of the global economy.

This report has demonstrated that the technology is superior to incumbents not merely by degree, but by category—shifting from chemically unstable polymers and fluids to the immutable stability of wide-bandgap crystalline Silicon Carbide. The impact of this shift will be felt in lighter electric vehicles, more efficient jet engines, and deeper geothermal wells.

Furthermore, the development of this patent serves as a pristine model for the R&D Tax Credit. It embodies the spirit of the incentive: high-risk, high-reward technical experimentation rooted in the hard sciences. With the strategic guidance of Swanson Reed, the economic value of this innovation can be maximized, ensuring that Arkansas remains a hub for the advanced materials that will define the rest of the 21st century.


Who We Are:

Swanson Reed is one of the largest Specialist R&D Tax Credit advisory firm in the United States. With offices nationwide, we are one of the only firms globally to exclusively provide R&D Tax Credit consulting services to our clients. We have been exclusively providing R&D Tax Credit claim preparation and audit compliance solutions for over 30 years. Swanson Reed hosts daily free webinars and provides free IRS CE and CPE credits for CPAs.

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The Research & Experimentation Tax Credit (or R&D Tax Credit), is a general business tax credit under Internal Revenue Code section 41 for companies that incur research and development (R&D) costs in the United States. The credits are a tax incentive for performing qualified research in the United States, resulting in a credit to a tax return. For the first three years of R&D claims, 6% of the total qualified research expenses (QRE) form the gross credit. In the 4th year of claims and beyond, a base amount is calculated, and an adjusted expense line is multiplied times 14%. Click here to learn more.

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