Oregon Patent of the Month – November 2025
The decades-long challenge of miniaturizing semiconductors just received a major boost. A new vertical chip architecture promises to revolutionize data density and speed. This innovation moves beyond traditional 2D scaling to unlock massive memory performance gains.
Advancing 3D Integration
Monolithic 3D Inc. recently secured U.S. Patent No. 12477752, titled ‘3D semiconductor memory devices and structures’. The patent describes a breakthrough in monolithic three-dimensional integrated circuits (3D ICs). This technique stacks memory control circuits and memory arrays directly on top of each other. The design creates a structure with ultra-dense, short vertical connections. This directly addresses the critical bottleneck of wire delay in conventional chips.
Impact on Performance and Cost
The new device integrates logic, such as a memory control circuit with digital-to-analog converters, below a multi-level memory array. This vertical configuration dramatically reduces the physical distance between components. This close proximity significantly cuts power consumption and boosts operational speed. Monolithic stacking offers superior vertical connectivity compared to older methods. The technology provides benefits equivalent to several generations of costly conventional scaling. This innovation secures a viable, cost-effective path for high-performance semiconductor development.
Learn More:
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